• Document: 100 Power Tips for FPGA Designers
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100 Power Tips for FPGA Designers Evgeni Stavinov Copyright © 2011 by Evgeni Stavinov. All rights reserved. No part of the material contained in this book, including all design, text, graphics, selection and arrangement of content and all other information may be reproduced or transmitted in any form or by any means, electronic or mechanical, without permission in writing from the author. Any unauthorized use of the material in this book without the prior permission of Evgeni Stavinov may violate copyright, trademark and other applicable laws. Third-Party Copyright Spartan, Virtex, Xilinx ISE, Zynq are trademarks of Xilinx Corporation. Incisive Palladium, NCSim are trademarks of Cadence Design Systems Inc. Riviera, Riviera-PRO, Active-HDL and HES are trademarks of Aldec, Inc. RocketDrive, RocketVision is a Trademark of GateRocket Corp. Synplify, Synplify Pro, Identify are trademarks of Synopsys Corporation. Stratix, Arria, and Cyclone are trademarks of Altera Corporation. All other copyrights and trademarks are the property of their respective owner. Limit of Liability/Disclaimer of Warranty To the fullest extent permitted at law, the publisher and the author are providing this book and its contents on an “as is” basis and make no (and expressly disclaims all) representations or warranties of any kind with respect to this book or its contents including, without limitation, warranties of merchantability and fitness for a particular purpose. In addition, the publisher and the author do not represent or warrant that the information in this book accurate, complete or current. Book Title: 100 Power Tips for FPGA Designers ISBN 978-1-4507-7598-4 Preface I’ve never thought of myself as a book writer. Over the course of my career I’ve written volumes of technical documentation, published several articles in technical magazines, and have done a lot of technical blogging. At some point I’ve accumulated a wealth of experience and knowledge in the area of FPGA design, and thought it was a good time to share it with a broader audience. Writing a book takes time, commitment, and discipline. It also requires a very different skill set. Unfortunately, many engineers, including myself, are trained to use programming languages better than natural languages. Despite all that, writing a book is definitely an intellectually rewarding experience. I would like to express my gratitude to all the people who have provided valuable ideas, reviewed technical contents, and edited the manuscript: my colleagues from SerialTek, former colleagues from Xilinx, technical bloggers, and many others. About the Author Evgeni Stavinov is a longtime FPGA user with more than 10 years of diverse design experience. Before becoming a hardware architect at SerialTek LLC, he held different engineering positions at Xilinx, LeCroy and CATC. Evgeni holds MS and BS degrees in electrical engineering from University of Southern California and Technion - Israel Institute of Technology. Evgeni is a creator of OutputLogic.com, a portal that offers different online productivity tools. Contents Introduction 1. Introduction 2. FPGA Landscape 3. FPGA Applications 4. FPGA Architecture 5. FPGA Project Tasks Efficient use of Xilinx FPGA design tools 6. Overview Of FPGA Design Tools 7. Xilinx FPGA Build Process 8. Using Xilinx Tools In Command-line Mode 9. Xilinx Environment Variables 10. Xilinx ISE Tool Versioning 11. Lesser Known Xilinx Tools 12. Understanding Xilinx Tool Reports Using Verilog HDL 13. Naming Conventions 14. Verilog Coding Style 15. Writing Synthesizable Code for FPGAs 16. Instantiation vs. Inference 17. Mixed Use of Verilog and VHDL 18. Verilog Versions: Verilog-95, Verilog-2001, and SystemVerilog 19. HDL Code Editors Design, Synthesis, and Physical Implementation 20. FPGA Clocking Resources 21. Designing a Clocking Scheme 22. Clock Domain Crossing 23. Clock Synchronization Circuits 24. Using FIFOs 25. Counters 26. Signed Arithmetic 27. State machines 28. Using Xilinx DSP48 primitive 29. Reset Scheme 30. Designing Shift Registers 31. Interfacing to external devices 32. Using Look-up Tables and Carry Chains 33. Designing Pipelines 34. Using Embedded Memory 35. Understanding FPGA Bitstream Structure 36. FPGA Configuration 37. FPGA Reconfiguration FPGA selection 38. Estimating Design Size 39. Estimating Design Speed 40. Estimating FPGA Power Consumption 41. Pin Assignment 42. Thermal Analysis 43. FPGA Cost Estimate 44. GPGPU vs. FPGA Migrating from ASIC to FPGA 45. ASIC to FPGA Migration Tasks 46. Differences Between ASIC and FPGA Designs 47. Selecting ASIC Emulation or Prototyping Platform 48. Partitioning an ASIC Design into Multiple FPGAs 49. Porting Clocks 50. Porting Latches 51. Porting Combinatorial Circuits 52. Porting Non-synthesizable Circuits 53. Modeling Memories 54. Porting Tri-state Logic 55.

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